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SX1230
Integrated Transmitter IC
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
6. Digital Control and Interface
The SX1230 has several operating modes, configuration parameters and internal status indicators which are stored in
internal registers. In MCU mode, all of these registers can be accessed by an external microcontroller via the SPI interface.
In stand alone mode, both the configuration information and the data to be transmitted, are stored in an external E 2 PROM.
The way that both the configuration and payload information is stored in the E 2 PROM must match the way the
configuration is defined in the internal registers. For a full description see Section 6.1.2.
6.1. Stand Alone Mode
6.1.1. State Machine Description
The stand alone mode is activated when the pin E2_Mode is tied to VDD. The SX1230 SPI interface is then configured in
master mode. The internal state machine of the SX1230 then carries out the following operations:
1) Immediately after power-up, the SPI interface reads the main configuration section in the E 2 PROM and then goes into
the ‘sleep’ operating mode (i.e. all blocks off).
2) Whilst in ‘sleep’ operating mode, when an edge is detected on any of the push-buttons PB[3:0], the chip wakes-up and
starts the RC oscillator (typical startup time ~100 μs).
3) The RC oscillator is used to clock a debounce timer which gives the logical push button input value after the
programmed delay. The frame section corresponding to the button value (1 to 15) is read from the E 2 PROM. At this point
additional, button specific, configuration information may be loaded. Otherwise, the configuration settings of 1) are used.
Using the appropriate configuration, the payload corresponding to the detected button press is then transmitted. The
payload transmission may be repeated up to 254 times.
4) When the frame has been transmitted, the pad PLL_LOCK goes low and the chip goes into SLEEP mode.
6.1.2. Memory Organization of the E 2 PROM
The memory map for stand alone mode is shown in Figure 6. The configuration information occupies the first 77 bytes, the
format of the configuration is {ADDR; VALUE} - therefore allowing up to 38 registers to be defined. Each push button
configuration is mapped directly to a location in the E 2 PROM - determined by the mappings given in Table 9 and the
variable section_size(5:0). The purpose of this variable, push button specific, section size is to allow the optimum use of
different sizes of external memory. Note that the maximum frame length is 64 bytes - this equates to a maximum E 2 PROM
size of 8 kbit. The influence of the section_size variable is illustrated in Figure 6.
The mapping of Table 9 permits up to 15 frames to be defined. Each section may contain both write_registers commands
and the payload to be transmitted. Thus allowing the dynamic configuration of settings such as output power and frequency
in response to a button push. Each section within the E 2 PROM must conform to the following format: {FIFO_ADDR;
REPEAT; LENGTH; VALUE_1; VALUE_2;...;VALUE_N}. Where VALUE_1... N is the user defined payload, REPEAT is the
number of times the frame is to be transmitted, LENGTH defines the number of bytes in the message and FIFO_ADDR =
0x95.
The push-buttons may need to be debounced before being read. The debouncer time constant is programmed by the
debounce_time(2:0) register which allows a range of debounce timer values to be accessed from 470 m s to 480 ms. An
SX1230, Revision 2 May 2009
?2008 Semtech Corp.
Page 15
www.semtech.com
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